In designing a synchronous circuit, it is an assumption that all memory devices use the “same clock”, the clock at each memory device switches at the same time (from high to low or from low to high), and all the rest combinational logic blocks share the same clock interval, so the setup time and hold time related to a clock to change state can be estimated by the memory devices, flip-flop, latch, etc. However, different routing lengths for the clock to be connected to a device and different input capacitance of a specific device make the above assumption unrealistic.
In FIG. 1, it is shown that the clock propagated from the clock source 0 to the sink 1 is faster than the clock propagated to the sink n, since the wire to sink n is longer than the wire to sink 1. A longer wire has a higher resistance and capacitance, which causes the time delay of the clock.
Currently, circuit designer uses the clock synthesis tools to generate a “balanced clock tree” which partitiones the fanout of a clock source 0 into several groups and puts each group as a branch of the clock source 0. Repeating the partition process stated above to the branches and so on, a clock tree is generated, as shown in FIG. 2. The clock synthesis tool can consider the wire RC and the gate input capacitance to make the routing from the clock source 0 to each sink the same length, so the clock to each sink has the same time delay. This idea has been applied to the most primitive H-Tree as well as to the most recent Steiner-Tree. Once the clock tree has been generated, the delay from the clock source 0 (root of the clock tree) to the sinks (leafs of the clock tree) should be the same.
If it is impossible by just using the “balanced clock tree” to compensate the time delay, a circiuit designer will insert buffers 20 into appropriate branches (hot branch) so as to creat a “buffer tree” as shown in FIG. 2. A buffer comprises of two inverters.
The above method assumes that the temperature and the voltage are both homogenous across the entire circuit all the time, i.e. the above method deems the tree is in a static state, but actually it is not true for an operating integrated circuit chip.
An operating integrated circuit chip has different surface temperature in different area, since some circuit blocks have more switching activities than the rest of the chip. The temperature differences will cause different mobility of the holes/electrons in the semiconductor device and also change the resistance of the metal wires. These phenomena also cause the time delay from the clock source 0 to the sinks. Moreover, circuitries generate more activities (more heat) will cause more voltage drop, the more voltage drop will make the local Vdd (power supply) lower than the rest parts of the chip so as to make some related devices (for instance:the inserted buffers) respond slower than other devices with a normal Vdd. Both the voltage drop and the temperature increasement make the above “balanced” clock tree un-balanced.
In order to take care of all the corner circuits with different temperature and voltage drop, the commercial CAD tools insert too many buffers in a clock tree, which makes the clock balance getting worst, since active devices (for instance: buffers) are effected by the voltage and temperature more than passive device (wire).